| ISBN: ISBN: 0-7695-0390-X
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| ISBN: DOI: 10.1109/ETW.1999.804415
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| |
| description |
An efficient deterministic BIST scheme based on partial scan chains
together with a scan selection algorithm tailored for BIST is
presented. The algorithm determines a minimum number of flipflops to
be scannable so that the remaining circuit has a pipeline-like
structure. Experiments show that scanning less flipflops may even
decrease the hardware overhead for the on-chip pattern generator
besides the classical advantages of partial scan such as less impact
on the system performance and less hardware overhead.
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| publisher |
Institute of Electrical and Electronics Engineers
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| type |
Text
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| Article in Proceedings
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| source |
In: Proceedings of the 4th IEEE European Test Workshop (ETW),
Constance, May 25-28, 1999, pp. 110-117
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| contributor |
Rechnerarchitektur (IFI)
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| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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